Via holes that extend onto the corresponding interconnect are opened in a semiconductor layer structure for contacting interconnects. It is all the more important that the filling of the via holes occurs in void-free fashion the smaller the cross section of the via holes becomes as a consequence of increasing miniaturization. A non-uniform filling of the via holes leads to a deterioration of the contact resistance.
A further increase in the packing density and a shortening of the connecting paths in semiconductor circuits is achieved by cubic integration. In cubic integration, semiconductor layer structures that contain the respective integrated circuit are respectively ground thin to a few 10 .mu.m and are arranged as a stack. The different semiconductor levels can thereby be composed of different substrate materials and/or can be fabricated in different technologies. Contacts must be formed through the semiconductor layer structures in a vertical direction. Such a component stack looks like a new semiconductor module viewed from the outside. It can be realized in a standard housing with a reduced number of connections, even though it comprises enhanced functionality.
The contacts between neighboring levels in cubic integration likewise occur via metal-filled via holes. The problem of void-free filling of via holes also arises here. Three-Dimensional ICs Project (Fiscal 1981-1990), Research and Development Association for Future Electron Devices, F.E.D., Tokyo, 1991, Chapter 2.1, incorporated herein, discloses a method with which vertical contacts between semiconductor layer structures arranged above one another in a stack can be realized. In the known method, tungsten pins having a cross section of approximately 3.times.3 .mu.m.sup.2 are formed on the upper side of a lower semiconductor layer structure. These tungsten pins project 1-2 .mu.m above the upper side of the lower semiconductor layer structure. Large-area depressions, which comprise a dimension of approximately 20.times.20 .mu.m.sup.2 are produced at a corresponding location of the underside of an immediately neighboring, upper semiconductor layer structure and are filled with an Au/In alloy. When the upper semiconductor layer structure and the lower semiconductor layer structure are stacked on top of one another, the tungsten pins immerse into these filled depressions. They are soldered at 300.degree. to 400.degree. C. For compensating surface topographies and in order to produce an additional mechanical connection between two semiconductor layer structures, the surfaces that meet one another are each respectively provided with a polyamide layer as an adhesive.
The thin tungsten pins must be deposited at extremely high temperatures. This leads to high stresses attacking in punctiform fashion in the corresponding semiconductor layer structure. In particular, stress cracks can thereby arise, particularly given stress-sensitive substrate materials such as GaAs or InP.